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fed500/Yosys

This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).

fed500/clblas-intel

clBLAS is a library that can make use of GPUs to offload basic linear algebra subroutine libraries. The version here is built using the Intel Beignet openCL runtime which will work on Intel CPUs with integrated GPUs.

fed500/clfft-intel

clFFT is a library that can make use of GPUs to offload FFT subroutine libraries. The version here is built using the Intel Beignet openCL runtime which will work on Intel CPUs with integrated GPUs.

fed500/clrng-intel

clRNG is a library that can make use of GPUs to offload random number generation subroutine libraries. The version here is built using the Intel Beignet openCL runtime which will work on Intel CPUs with integrated GPUs.

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python-mxcubecore

Project: @copr/PyPI

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ramalama

Project: packit/containers-ramalama-1984

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python-checkdmarc

Project: @copr/PyPI

Build: 9648406

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python-cluster-tools

Project: @copr/PyPI

Build: 9648411

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