rezso/HDL

Project ID: 46761

Build 2906185

General Information

Status:
succeeded - Successfully built.
Submitted:
2021-10-24 21:16 UTC (a month ago)
Started:
2021-10-24 21:17 UTC (a month ago)
Finished:
2021-10-24 21:22 UTC (a month ago)
Build time:
5 minutes
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20211015.git267fc38.fc36
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20211015.git267fc38.fc36.src.rpm