rezso/HDL

Project ID: 46761

Build 3458726

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-02-12 00:59 UTC (2 years ago)
Started:
2022-02-12 01:00 UTC (2 years ago)
Finished:
2022-02-12 01:06 UTC (2 years ago)
Build time:
5 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
fpga-interchange-schema
Version:
0.0-20220211.0.git3b27223f
Source Type:
SRPM or .spec file upload
File Name:
fpga-interchange-schema-0.0-20220211.0.git3b27223f.src.rpm