rezso/HDL

Project ID: 46761

Build 3891183

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-03-28 09:25 UTC (2 years ago)
Started:
2022-03-28 09:25 UTC (2 years ago)
Finished:
2022-03-28 09:32 UTC (2 years ago)
Build time:
6 minutes
Build timeout:
5 hours
Networking enabled:
True
Batch:
31138
Directory:
HDL
Built by:
rezso

Source

Package:
fpga-interchange-schema
Version:
0.0-20220221.0.git9a48ae4d
Source Type:
SRPM or .spec file upload
File Name:
fpga-interchange-schema-0.0-20220221.0.git9a48ae4d.src.rpm