rezso/HDL

Project ID: 46761

Build 3891257

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-03-28 09:27 UTC (2 years ago)
Started:
2022-03-28 09:33 UTC (2 years ago)
Finished:
2022-03-28 09:38 UTC (2 years ago)
Build time:
5 minutes
Build timeout:
5 hours
Networking enabled:
True
Batch:
31139
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.9-20220325.0.gitc12aff88
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.9-20220325.0.gitc12aff88.src.rpm