rezso/HDL

Project ID: 46761

Build 4395453

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-11 01:24 UTC (1 year, 10 months ago)
Started:
2022-05-11 01:26 UTC (1 year, 10 months ago)
Finished:
2022-05-11 01:35 UTC (1 year, 10 months ago)
Build time:
9 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20220510.0.git63291ba5
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20220510.0.git63291ba5.src.rpm