rezso/HDL

Project ID: 46761

Build 4413593

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-15 01:27 UTC (1 year, 11 months ago)
Started:
2022-05-15 01:28 UTC (1 year, 11 months ago)
Finished:
2022-05-15 02:06 UTC (1 year, 11 months ago)
Build time:
38 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
11.0-20220512.0.gite67a796a
Source Type:
SRPM or .spec file upload
File Name:
iverilog-11.0-20220512.0.gite67a796a.src.rpm