rezso/HDL

Project ID: 46761

Build 4559639

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-06-23 18:54 UTC (1 year, 9 months ago)
Started:
2022-06-23 18:59 UTC (1 year, 9 months ago)
Finished:
2022-06-23 19:09 UTC (1 year, 9 months ago)
Build time:
9 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20220527.2.git27fc1db2
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20220527.2.git27fc1db2.src.rpm