rezso/HDL

Project ID: 46761

Build 4597374

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-07-05 01:24 UTC (1 year, 9 months ago)
Started:
2022-07-05 01:25 UTC (1 year, 9 months ago)
Finished:
2022-07-05 01:32 UTC (1 year, 9 months ago)
Build time:
7 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
fpga-interchange-schema
Version:
0.0-20220704.0.gitc985b464
Source Type:
SRPM or .spec file upload
File Name:
fpga-interchange-schema-0.0-20220704.0.gitc985b464.src.rpm