rezso/HDL

Project ID: 46761

Build 7721379

General Information

Status:
succeeded - Successfully built.
Submitted:
2024-07-10 01:00 UTC (5 months ago)
Started:
2024-07-10 01:01 UTC (5 months ago)
Finished:
2024-07-10 01:44 UTC (5 months ago)
Build time:
43 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20240709.0.gitcb6544fa
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20240709.0.gitcb6544fa.src.rpm