rezso/HDL

Project ID: 46761

Build 7920572

General Information

Status:
succeeded - Successfully built.
Submitted:
2024-08-19 13:45 UTC (29 days ago)
Started:
2024-08-19 13:46 UTC (29 days ago)
Finished:
2024-08-19 13:56 UTC (29 days ago)
Build time:
10 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20221019.4.git04a02101
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20221019.4.git04a02101.fc42.src.rpm