rezso/HDL

Project ID: 46761

Build 8320487

General Information

Status:
succeeded - Successfully built.
Submitted:
2024-11-28 00:50 UTC (2 months ago)
Started:
2024-11-28 00:51 UTC (2 months ago)
Finished:
2024-11-28 00:58 UTC (2 months ago)
Build time:
6 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20241127.0.gitb7451197
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20241127.0.gitb7451197.src.rpm