rezso/HDL

Project ID: 46761

Build 8451476

General Information

Status:
succeeded - Successfully built.
Submitted:
2024-12-28 00:45 UTC (2 months ago)
Started:
2024-12-28 00:45 UTC (2 months ago)
Finished:
2024-12-28 00:52 UTC (2 months ago)
Build time:
7 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20241227.0.gitabaa32f7
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20241227.0.gitabaa32f7.src.rpm