rezso/HDL

Project ID: 46761

Build 8677452

General Information

Status:
succeeded - Successfully built.
Submitted:
2025-02-21 00:47 UTC (a day ago)
Started:
2025-02-21 00:48 UTC (a day ago)
Finished:
2025-02-21 00:55 UTC (a day ago)
Build time:
7 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20250217.0.git99580cd0
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20250217.0.git99580cd0.src.rpm