rezso/HDL

Project ID: 46761

Build 9271730

General Information

Status:
succeeded - Successfully built.
Submitted:
2025-07-14 11:19 UTC (4 days ago)
Started:
2025-07-14 11:19 UTC (4 days ago)
Finished:
2025-07-14 11:25 UTC (4 days ago)
Build time:
6 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20250713.0.gite55d9454
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20250713.0.gite55d9454.src.rpm