rezso/VLSI

Project ID: 47112

Build 4144274

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-09 16:05 UTC (2 years ago)
Started:
2022-04-09 16:06 UTC (2 years ago)
Finished:
2022-04-09 16:18 UTC (2 years ago)
Build time:
11 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.04.08.02.45.18-20220407.2.gitb7370865
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.04.08.02.45.18-20220407.2.gitb7370865.src.rpm