rezso/VLSI

Project ID: 47112

Build 4189553

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-12 08:03 UTC (2 years ago)
Started:
2022-04-12 10:10 UTC (2 years ago)
Finished:
2022-04-12 10:29 UTC (2 years ago)
Build time:
19 minutes
Build timeout:
2 days
Networking enabled:
True
Batch:
33205
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.04.08.02.45.18-20220411.0.git7891c2c8
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.04.08.02.45.18-20220411.0.git7891c2c8.src.rpm