rezso/VLSI

Project ID: 47112

Build 4205324

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-13 07:51 UTC (2 years ago)
Started:
2022-04-13 12:07 UTC (2 years ago)
Finished:
2022-04-13 12:18 UTC (2 years ago)
Build time:
11 minutes
Build timeout:
5 hours
Networking enabled:
True
Batch:
33350
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.04.08.02.45.18-20220413.0.gitfc96d12d
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.04.08.02.45.18-20220413.0.gitfc96d12d.src.rpm