rezso/VLSI

Project ID: 47112

Build 4369988

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-06 10:57 UTC (1 year, 10 months ago)
Started:
2022-05-06 10:59 UTC (1 year, 10 months ago)
Finished:
2022-05-06 11:18 UTC (1 year, 10 months ago)
Build time:
19 minutes
Build timeout:
5 hours
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.05.05.02.01.30-20220504.2.git0c2d66a2
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.05.05.02.01.30-20220504.2.git0c2d66a2.src.rpm