rezso/VLSI

Project ID: 47112

Build 4621563

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-07-10 12:29 UTC (1 year, 8 months ago)
Started:
2022-07-10 12:30 UTC (1 year, 8 months ago)
Finished:
2022-07-10 12:42 UTC (1 year, 8 months ago)
Build time:
11 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.07.02.01.38.08-20220705.0.gitb718fd06
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.07.02.01.38.08-20220705.0.gitb718fd06.src.rpm