rezso/VLSI

Project ID: 47112

Build 5231919

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-01-14 18:31 UTC (1 year, 2 months ago)
Started:
2023-01-14 18:32 UTC (1 year, 2 months ago)
Finished:
2023-01-14 18:45 UTC (1 year, 2 months ago)
Build time:
12 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2023.01.12-20230111.0.git06b26813
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.01.12-20230111.0.git06b26813.src.rpm