rezso/VLSI

Project ID: 47112

Build 5282312

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-01-22 01:44 UTC (1 year, 9 months ago)
Started:
2023-01-22 01:46 UTC (1 year, 9 months ago)
Finished:
2023-01-22 02:03 UTC (1 year, 9 months ago)
Build time:
16 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2023.01.20-20230119.0.git0b94d33d
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.01.20-20230119.0.git0b94d33d.src.rpm