rezso/VLSI

Project ID: 47112

Build 6027408

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-06-09 01:51 UTC (1 year, 6 months ago)
Started:
2023-06-09 02:27 UTC (1 year, 6 months ago)
Finished:
2023-06-09 02:42 UTC (1 year, 6 months ago)
Build time:
14 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2023.06.08-20230607.0.git85e9dc67
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.06.08-20230607.0.git85e9dc67.src.rpm