rezso/VLSI

Project ID: 47112

Build 6112520

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-06-26 01:57 UTC (1 year, 4 months ago)
Started:
2023-06-26 02:37 UTC (1 year, 4 months ago)
Finished:
2023-06-26 03:08 UTC (1 year, 4 months ago)
Build time:
31 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2023.06.23-20230622.0.gitaeef4d05
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.06.23-20230622.0.gitaeef4d05.src.rpm