rezso/VLSI

Project ID: 47112

Build 6764730

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-12-17 10:03 UTC (1 year, 2 days ago)
Started:
2023-12-17 10:03 UTC (1 year, 2 days ago)
Finished:
2023-12-17 10:10 UTC (1 year, 2 days ago)
Build time:
6 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Resubmitted from:
6763233
Built by:
rezso

Source

Package:
openlane
Version:
2023.12.13-20231212.0.git66e938bc
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.12.13-20231212.0.git66e938bc.src.rpm