rezso/VLSI

Project ID: 47112

Build 4397968

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-11 16:50 UTC (2 years ago)
Started:
2022-05-11 17:53 UTC (2 years ago)
Finished:
2022-05-11 18:08 UTC (2 years ago)
Build time:
15 minutes
Build timeout:
5 hours
Networking enabled:
True
Batch:
37569
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.05.11.01.53.47-20220509.0.git0c611a34.fc37
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.05.11.01.53.47-20220509.0.git0c611a34.fc37.src.rpm