rezso/VLSI

Project ID: 47112

Build 4571214

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-06-28 14:09 UTC (1 year, 11 months ago)
Started:
2022-06-28 14:10 UTC (1 year, 11 months ago)
Finished:
2022-06-28 14:22 UTC (1 year, 11 months ago)
Build time:
11 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.06.27.01.36.21-20220626.0.git83b61459
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.06.27.01.36.21-20220626.0.git83b61459.src.rpm