rezso/VLSI

Project ID: 47112

Build 4628848

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-07-11 18:17 UTC (1 year, 11 months ago)
Started:
2022-07-11 18:18 UTC (1 year, 11 months ago)
Finished:
2022-07-11 18:30 UTC (1 year, 11 months ago)
Build time:
12 minutes
Build timeout:
5 hours
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.07.02.01.38.08-20220705.1.gitb718fd06
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.07.02.01.38.08-20220705.1.gitb718fd06.src.rpm