rezso/VLSI

Project ID: 47112

Build 3081341

General Information

Status:
succeeded - Successfully built.
Submitted:
2021-12-24 14:56 UTC (2 years ago)
Started:
2021-12-24 14:56 UTC (2 years ago)
Finished:
2021-12-24 15:00 UTC (2 years ago)
Build time:
3 minutes
Build timeout:
5 hours
Networking enabled:
False
Directory:
VLSI
Built by:
rezso

Source

Package:
netgen
Version:
1.5.213-20211219.gitab614b6.fc36
Source Type:
SRPM or .spec file upload
File Name:
netgen-1.5.213-20211219.gitab614b6.fc36.src.rpm