rezso/VLSI

Project ID: 47112

Build 3121846

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-01-02 21:36 UTC (2 years ago)
Started:
2022-01-02 21:37 UTC (2 years ago)
Finished:
2022-01-02 22:52 UTC (2 years ago)
Build time:
an hour
Build timeout:
5 hours
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openroad
Version:
2.0-20220101.0.git789d5b3e.fc36
Source Type:
SRPM or .spec file upload
File Name:
openroad-2.0-20220101.0.git789d5b3e.fc36.src.rpm