rezso/VLSI

Project ID: 47112

Build 3938276

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-01 18:20 UTC (2 years ago)
Started:
2022-04-01 18:22 UTC (2 years ago)
Finished:
2022-04-01 18:41 UTC (2 years ago)
Build time:
19 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.03.31.02.35.19-20220401.0.git2f276c62
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.03.31.02.35.19-20220401.0.git2f276c62.src.rpm