rezso/VLSI

Project ID: 47112

Build 4451008

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-27 08:07 UTC (1 year, 11 months ago)
Started:
2022-05-27 08:08 UTC (1 year, 11 months ago)
Finished:
2022-05-27 08:53 UTC (1 year, 11 months ago)
Build time:
44 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.05.26.01.40.55-20220525.0.git2653e6e4
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.05.26.01.40.55-20220525.0.git2653e6e4.src.rpm