rezso/VLSI

Project ID: 47112

Build 4545943

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-06-19 01:25 UTC (1 year, 10 months ago)
Started:
2022-06-19 01:26 UTC (1 year, 10 months ago)
Finished:
2022-06-19 02:01 UTC (1 year, 10 months ago)
Build time:
35 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.06.15.01.35.48-20220618.0.gita9883335
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.06.15.01.35.48-20220618.0.gita9883335.src.rpm