rezso/VLSI

Project ID: 47112

Build 4628840

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-07-11 18:09 UTC (1 year, 9 months ago)
Started:
2022-07-11 18:09 UTC (1 year, 9 months ago)
Finished:
2022-07-11 18:12 UTC (1 year, 9 months ago)
Build time:
3 minutes
Build timeout:
5 hours
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
tcllib
Version:
1.19-3
Source Type:
SRPM or .spec file upload
File Name:
tcllib-1.19-3.src.rpm

Results

Source state:
succeeded
Source build logs:
builder-live.log.gz , backend.log.gz
Built Packages:
tcllib 1.19
Chroot Name Dist Git Source Build Time Logs State
epel-9-aarch64 2f32111 3 minutes builder-live.log.gz , backend.log.gz succeeded
epel-9-ppc64le 2f32111 2 minutes builder-live.log.gz , backend.log.gz succeeded
epel-9-x86_64 2f32111 a minute builder-live.log.gz , backend.log.gz succeeded