rezso/VLSI

Project ID: 47112

Build 4695830

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-08-01 20:57 UTC (1 year, 8 months ago)
Started:
2022-08-01 20:58 UTC (1 year, 8 months ago)
Finished:
2022-08-01 21:09 UTC (1 year, 8 months ago)
Build time:
11 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2022.07.30-20220729.0.git4476a584
Source Type:
SRPM or .spec file upload
File Name:
openlane-2022.07.30-20220729.0.git4476a584.src.rpm