rezso/VLSI

Project ID: 47112

Build 5198594

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-01-04 01:37 UTC (1 year, 3 months ago)
Started:
2023-01-04 01:38 UTC (1 year, 3 months ago)
Finished:
2023-01-04 01:54 UTC (1 year, 3 months ago)
Build time:
15 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2023.01.03-20230102.0.gite570a6a5
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.01.03-20230102.0.gite570a6a5.src.rpm