rezso/VLSI

Project ID: 47112

Build 5992961

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-06-01 02:09 UTC (11 months ago)
Started:
2023-06-01 02:26 UTC (11 months ago)
Finished:
2023-06-01 02:41 UTC (11 months ago)
Build time:
14 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
VLSI
Built by:
rezso

Source

Package:
openlane
Version:
2023.06.01-20230531.0.gite910d115
Source Type:
SRPM or .spec file upload
File Name:
openlane-2023.06.01-20230531.0.gite910d115.src.rpm