rezso/HDL

Project ID: 46761

Build 4349995

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-30 01:25 UTC (2 years ago)
Started:
2022-04-30 01:26 UTC (2 years ago)
Finished:
2022-04-30 01:31 UTC (2 years ago)
Build time:
5 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20220428.0.git1d7ca360
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20220428.0.git1d7ca360.src.rpm