rezso/HDL

Project ID: 46761

Build 4423657

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-19 01:29 UTC (1 year, 11 months ago)
Started:
2022-05-19 01:29 UTC (1 year, 11 months ago)
Finished:
2022-05-19 01:35 UTC (1 year, 11 months ago)
Build time:
5 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20220514.0.git5c059c52
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20220514.0.git5c059c52.src.rpm