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rezso/HDL

Project ID: 46761

Build 2931540

General Information

Status:
succeeded - Successfully built.
Submitted:
2021-11-05 18:20 UTC (1 year, 1 month ago)
Started:
2021-11-05 18:24 UTC (1 year, 1 month ago)
Finished:
2021-11-05 18:44 UTC (1 year, 1 month ago)
Build time:
19 minutes
Build timeout:
5 hours
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
11.0-20211104.git0e3682a1.fc36
Source Type:
SRPM or .spec file upload
File Name:
iverilog-11.0-20211104.git0e3682a1.fc36.src.rpm