rezso/HDL

Project ID: 46761

Build 2957812

General Information

Status:
succeeded - Successfully built.
Submitted:
2021-11-14 14:34 UTC (1 year, 23 days ago)
Started:
2021-11-14 14:36 UTC (1 year, 23 days ago)
Finished:
2021-11-14 14:52 UTC (1 year, 23 days ago)
Build time:
15 minutes
Build timeout:
5 hours
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
11.0-20211112.git71c36d12.fc36
Source Type:
SRPM or .spec file upload
File Name:
iverilog-11.0-20211112.git71c36d12.fc36.src.rpm