rezso/HDL

Project ID: 46761

Build 3047066

General Information

Status:
succeeded - Successfully built.
Submitted:
2021-12-14 21:17 UTC (11 months ago)
Started:
2021-12-14 21:17 UTC (11 months ago)
Finished:
2021-12-14 21:47 UTC (11 months ago)
Build time:
29 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
11.0-20211213.git668f9850.fc36
Source Type:
SRPM or .spec file upload
File Name:
iverilog-11.0-20211213.git668f9850.fc36.src.rpm