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rezso/HDL

Project ID: 46761

Build 3938712

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-02 01:03 UTC (8 months ago)
Started:
2022-04-02 01:05 UTC (8 months ago)
Finished:
2022-04-02 01:19 UTC (8 months ago)
Build time:
14 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
11.0-20220327.0.gitd480c4d7
Source Type:
SRPM or .spec file upload
File Name:
iverilog-11.0-20220327.0.gitd480c4d7.src.rpm