rezso/HDL

Project ID: 46761

Build 6099019

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-06-20 20:03 UTC (1 year, 25 days ago)
Started:
2023-06-20 20:03 UTC (1 year, 25 days ago)
Finished:
2023-06-20 20:16 UTC (1 year, 25 days ago)
Build time:
13 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20230616.0.gita43e7e85
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20230616.0.gita43e7e85.src.rpm