rezso/HDL

Project ID: 46761

Build 6120429

General Information

Status:
succeeded - Successfully built.
Submitted:
2023-06-28 01:52 UTC (1 year, 17 days ago)
Started:
2023-06-28 01:53 UTC (1 year, 17 days ago)
Finished:
2023-06-28 02:02 UTC (1 year, 17 days ago)
Build time:
8 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
iverilog
Version:
13.0-20230626.0.gita3f1aded
Source Type:
SRPM or .spec file upload
File Name:
iverilog-13.0-20230626.0.gita3f1aded.src.rpm