Description
Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
Installation Instructions
The latest
Active Releases
The following unofficial repositories are provided as-is by owner of this project. Contact the owner directly for bugs or issues (IE: not bugzilla).
| Release | Architectures | Repo Download |
|---|---|---|
Fedora 38
|
x86_64 (18)* | Fedora 38 (0 downloads) |
|
Fedora 39
|
x86_64 (19)* | Fedora 39 (40 downloads) |
|
Fedora 40
|
x86_64 (15)* | Fedora 40 (21 downloads) |
|
Fedora 41
|
x86_64 (10)* | Fedora 41 (8 downloads) |
|
Fedora rawhide
|
x86_64 (17)* | Fedora rawhide (55 downloads) |
* Total number of downloaded packages.
Quick Enable
#> dnf copr enable s-kro/verilator
More info about enabling Copr repositories