Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
The following unofficial repositories are provided as-is by owner of this project. Contact the owner directly for bugs or issues (IE: not bugzilla).
|Fedora 37||x86_64 (0)*||Fedora 37 (7 downloads)|
|Fedora 38||x86_64 (0)*||Fedora 38 (6 downloads)|
|Fedora 39||x86_64 (0)*||Fedora 39 (7 downloads)|
|Fedora rawhide||x86_64 (0)*||Fedora rawhide (7 downloads)|
* Total number of packages downloaded in the last seven days.