vowstar/verilator

Description

Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.

Installation Instructions

yum install yum-plugin-copr
yum copr enable vowstar/verilator
yum install verilator

or

dnf install dnf-plugins-core
dnf copr enable vowstar/verilator
dnf install verilator

Active Releases

The following unofficial repositories are provided as-is by owner of this project. Contact the owner directly for bugs or issues (IE: not bugzilla).

Release	Architectures	Repo Download
Centos-stream 8	x86_64 (0)*	Centos-stream 8 (17 downloads)
Centos-stream 9	x86_64 (0)*	Centos-stream 9 (14 downloads)
EPEL 8	x86_64 (24)*	EPEL 8 (14 downloads)
EPEL 9	x86_64 (3)*	EPEL 9 (14 downloads)
Fedora 40	x86_64 (0)*	Fedora 40 (2 downloads)
Fedora rawhide	x86_64 (0)*	Fedora rawhide (16 downloads)
openEuler 20.03	x86_64 (0)*	openEuler 20.03 (20 downloads)
openEuler 22.03	x86_64 (0)*	openEuler 22.03 (15 downloads)
Rhel 8	x86_64 (0)*	Rhel 8 (14 downloads)
Rhel 9	x86_64 (0)*	Rhel 9 (19 downloads)

* Total number of downloaded packages.