Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
yum install yum-plugin-copr yum copr enable vowstar/verilator yum install verilator
dnf install dnf-plugins-core dnf copr enable vowstar/verilator dnf install verilator
The following unofficial repositories are provided as-is by owner of this project. Contact the owner directly for bugs or issues (IE: not bugzilla).
|Centos-stream 8||x86_64 (0)*||Centos-stream 8 (5 downloads)|
|Centos-stream 9||x86_64 (0)*||Centos-stream 9 (4 downloads)|
|EPEL 8||x86_64 (2)*||EPEL 8 (6 downloads)|
|EPEL 9||x86_64 (0)*||EPEL 9 (4 downloads)|
|Fedora rawhide||x86_64 (0)*||Fedora rawhide (5 downloads)|
|openEuler 20.03||x86_64 (0)*||openEuler 20.03 (5 downloads)|
|openEuler 22.03||x86_64 (0)*||openEuler 22.03 (4 downloads)|
|Rhel 8||x86_64 (0)*||Rhel 8 (4 downloads)|
|Rhel 9||x86_64 (0)*||Rhel 9 (5 downloads)|
* Total number of packages downloaded in the last seven days.