rezso/HDL

Project ID: 46761

Build 4094278

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-07 01:07 UTC (7 months ago)
Started:
2022-04-07 01:08 UTC (7 months ago)
Finished:
2022-04-07 01:14 UTC (7 months ago)
Build time:
6 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20220406.0.git3ab487ca
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20220406.0.git3ab487ca.src.rpm